1. Field
The disclosed technology generally relates to a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function.
2. Description of the Related Technology
Some semiconductor devices have complementary metal-oxide-semiconductor field effect transistors (MOSFETs). A MOSFET device can be characterized by a threshold voltage (VT), which refers to a voltage on a gate of the MOSFET which renders the channel of the MOSFET conductive. Processes for fabricating the complementary MOSFETs, also referred to as complementary MOS (CMOS) processes, include processes for fabricating both n-channel (NMOS) and p-channel (PMOS) MOS transistors. The threshold voltage VT of a MOSFET is influenced by, among other parameters, what is known in the industry and referred to herein as an effective work function (WFeff). The effective work function refers to the work function of a gate electrode which takes into account of a flat band voltage (Vfb) of the gate stack while ignoring any contribution to the same Vfb from charges or dipoles in the gate-stack. WFeff therefore, may not be equivalent to the metal vacuum work function which is a physical characteristic of the metal. In some CMOS technologies, threshold voltage (VT) values of the PMOS and NMOS MOSFETs can be engineered by independently controlling the effective work function of the respective PMOS and NMOS gate materials (gate stacks) and their corresponding channel regions through relatively independent channel processing and gate processing. Because the gate dielectric can affect the channel regions, both the gate dielectric (including, e.g., a host dielectric and possible different capping layers) and the gate electrode (including, e.g., at least one metal layer) determine the effective work function (WFeff) of the gate stack. Moreover, the gate processing itself (i.e. the sequence of the different processes and/or the thermal treatments applied) may have an influence on the effective work function of the gate stack (device) (WFeff). By adjusting the WFeff, the VT of the device can be adjusted. Generally, a higher WFeff results in higher/lower nMOS/pMOS VT respectively, while a lower WFeff results in lower/higher nMOS/pMOS VT, respectively.
For some applications, CMOS devices having different VT's are formed on the same substrate, for instance two, three, four or more types of CMOS devices each having different VT's. Such devices are referred to as multi-VT devices.
Traditionally, multi-VT has been implemented by implantation of for instance B or P into the channel of the devices. However, with the emergence of FINFET devices and the scaling of the fin widths, especially fin widths smaller than 10 nm, the impact of doping on the VT is reduced. Additionally, high channel doping levels result in lower mobility due to scattering and worse mismatch due to dopant fluctuations.
Therefore, there is a need in industry for alternative multi-VT solutions.